Image Sensor Papers at VLSI Symposia 2017

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VLSI Symposia to be held on June 5-8, 2017 in Kyoto, Japan, presents its programs with a significant image sensors content:

An All Pixel PDAF CMOS Image Sensor with 0.64μm×1.28μm Photodiode Separated by Self-Aligned In-Pixel Deep Trench Isolation for High AF Performance,
S. Choi, K. Lee, J. Yun, S. Choi, S. Lee, J. Park, E. S. Shim, J. Pyo, B. Kim, M. Jung, Y. Lee, K. Son, S. Jung, T.-S. Wang, Y. Choi, D.-K. Min, J. Im, C.-R. Moon, D. Lee and D. Chang, Samsung, Korea
We present a CMOS image sensor (CIS) with phase detection auto-focus (PDAF) in all pixels. The size of photodiode (PD) is 0.64μm by 1.28μm, the smallest ever reported and two PDs compose a single pixel. Inter PD isolation was fabricated by deep trench isolation (DTI) process in order to obtain an accurate AF performance. The layout and depth of DTI was optimized in order to eliminate side effects and maximize the performance even at extremely low light condition up to 1lux. In particular the AF performance remains comparable to that of 0.70μm dual PD CIS. By using our unique technology, it seems plausible to scale further down the size of pixels in dual PD CIS without sacrificing AF performance.

A Shutter-Less Micro-Bolometer Thermal Imaging System Using Multiple Digital Correlated Double Sampling for Mobile Applications,
S. Park, T. Cho, M. Kim, H. Park and K. Lee, KAIST and Seoul National Univ. of Science and Technology, Korea
A micro-bolometer focal plane array (MBFPA)-based long wavelength Infra-red thermal imaging sensor is presented. The proposed multiple digital correlated double sampling (MD-CDS) readout method employing newly designed reference-cell greatly reduces PVT variation-induced fixed pattern noise (FPN) and as a result features much relaxed calibration process, easier TEC-less operation and Shutter-less operation. The readout IC and MBFPA was fabricated in 0.35um CMOS and amorphous silicon MEMS process respectively. The fabricated MBFPA thermal imaging sensor has NETD performance of 0.1 kelvin even though the mechanical shutter is not used.

Trantenna: Monolithic Transistor-Antenna Device for Real-Time THz Imaging System,
M. W. Ryu, R. Patel, S. H. Ahn, H. J. Jeon, M. S. Choe, E. Choi, K. J. Han and K. R. Kim, UNIST, Korea
We report a circular-shape monolithic transistor-antenna (trantenna) for high-performance plasmonic terahertz (THz) detector. By designing an asymmetric transistor on a ring-type metal-gate structure, more enhanced (45 times) channel charge asymmetry has been obtained in comparison with a bar-type asymmetric transistor of our previous work. In addition, by exploiting ring-type transistor itself as a monolithic circular patch antenna, which is designed for a 0.12-THz resonance frequency, we demonstrated the highly-enhanced responsivity (Rv) > 1 kV/W (x 5) and reduced noise-equivalent power (NEP) < 10 pW/Hz0.5 (x 1/10).

Chip-Scale Fluorescence Imager for In Vivo Microscopic Cancer Detection,
E. P. Papageorgiou, B. E. Boser and M. Anwar, Univ. of California, Berkeley and Univ. of California, San Francisco, USA
Modern cancer treatment faces the pervasive challenge of identifying microscopic cancer foci in vivo, but no imaging device exists with the ability to identify these cells intraoperatively, where they can be removed. We introduce a novel CMOS sensor that identifies foci of less than 200 cancer cells labeled with fluorescent biomarkers in 50ms. The sensor’s miniature size enables manipulation within a small, morphologically complex, tumor cavity. Recognizing that focusing optics traditionally used in fluorescence imagers present a barrier to miniaturization, we integrate stacked CMOS metal layers above each photodiode to form angle-selective gratings, rejecting background light and deblurring the image. A high-gain capacitive transimpedance amplifier based pixel with 8.2V/s per pW sensitivity and a dark current minimization circuit enables rapid detection of microscopic clusters of 100s of tumor cells with minimal error.

A 4.1Mpix 280fps Stacked CMOS Image Sensor with Array-Parallel ADC Architecture for Region Control,
T. Takahashi, Y. Kaji, Y. Tsukuda, S. Futami, K. Hanzawa, T. Yamauchi, P. W. Wong, F. Brady, P. Holden, T. Ayers, K. Mizuta, S. Ohki, K. Tatani, T. Nagano, H. Wakabayashi, and Y. Nitta, Sony, Japan and Sony, USA
A 4.1Mpix 280fps stacked CMOS image sensor with array-parallel ADC architecture is developed for region control applications. The combination of an active reset scheme and frame correlated double sampling (CDS) operation cancels Vth variation of pixel amplifier transistors and kTC noise. The sensor utilizes a floating diffusion (FD) based back-illuminated (BI) global shutter (GS) pixel with 4.2e-rms readout noise. An intelligent sensor system with face detection and high resolution region-of-interest (ROI) output is demonstrated with significantly low data bandwidth and low ADC power dissipation by utilizing a flexible area access function.

A 256 Energy Bin Spectrum X-Ray Photon-Counting Image Sensor Providing 8Mcounts/s/pixel and On-Chip Charge Sharing, Charge Induction and Pile-Up Corrections,
A. Peizerat, J.-P. Rostaing, P. Ouvrier-Buffet, S. Stanchina, P. Radisson, and E. Marché, CEA-LETI and Multix, France
To achieve better and faster material discrimination in applications like security inspection, X-Ray image sensors giving a highly resolved energy spectrum per pixel are required. In this paper, a new pixel architecture for spectral imaging is presented, exhibiting a 256 bin spectrum per pixel in a single image duration, up to two orders of magnitude higher than previous works. A prototype circuit, composed of 4x8 pixels of 756μmx800μm and hybridized to a CdTe crystal, was fabricated in a 0.13μm process. Our pixel architecture has been measured at 8 Mcounts/s/pixel while embedding on-chip charge sharing, charge induction and pile-up corrections.

A 0.61 E- Noise Global Shutter CMOS Image Sensor with Two-Stage Charge Transfer Pixels,
K. Yasutomi, M. W. Seo, M. Kamoto, N. Teranishi and S. Kawahito, Shizuoka Univ., Japan
A low-noise global shutter (GS) CMOS image sensor (CIS) with two-stage charge transfer (2-CT) structure is presented. The low-noise wide dynamic range performance of the proposed pixel has been demonstrated by using column-parallel folding integration (FI)/cyclic ADCs. The GS image sensor with 5.6μm-pitch 1200 x 900 pixels is implemented with a 0.11μm CIS technology. The noise and dynamic range are measured to be 0.61 erms and 81 dB, respectively.

224-ke Saturation Signal Global Shutter CMOS Image Sensor with In-Pixel Pinned Storage and Lateral Overflow Integration Capacitor,
Y. Sakano, S. Sakai, Y. Tashiro, Y. Kato, K. Akiyama, K. Honda, M. Sato, M. Sakakibara, T. Taura, K. Azami, T. Hirano, Y. Oike, Y. Sogo, T. Ezaki, T. Narabu, T. Hirayama, and S. Sugawa, Sony and Tohoku Univ., Japan
The required incorporation of an additional in-pixel retention node for global shutter complementary metal-oxide semiconductor (CMOS) image sensors means that achieving a large saturation signal presents a challenge. This paper reports a 3.875-μm pixel single exposure global shutter CMOS image sensor with an in-pixel pinned storage (PST) and a lateral-overflow integration capacitor (LOFIC), which extends the saturation signal to 224 ke, thereby enabling the saturation signal per unit area to reach 14.9 ke/μm2. This pixel can assure a large saturation signal by using a LOFIC for accumulation without degrading the image quality under dark and low illuminance conditions owing to the PST.

320x240 Back-Illuminated 10µm CAPD Pixels for High Speed Modulation Time-of-Flight CMOS Image Sensor,
Y. Kato, T. Sano, Y. Moriyama, S. Maeda, T. Yamazaki, A. Nose, K. Shina, Y. Yasu, W. van der Tempel, A. Ercan and Y. Ebiko, Sony, Japan and SoftKinetic, Belgium
A 320x240 back-illuminated Time-of-Flight CMOS image sensor with 10µm CAPD pixels has been developed. The backilluminated (BI) pixel structure maximizes the fill factor, allows for flexible transistor position and makes the light path independent of the metal layer. In addition, the CAPD pixel, which is optimized for high speed modulation, results in 80% modulation contrast at 100MHz modulation frequency.

An Imager Using 2-D Single-Photon Avalanche Diode Array in 0.18-μm CMOS for Automotive LIDAR Application,
H. Akita*, I. Takai, K. Azuma, T. Hata and N. Ozaki, DENSO and Toyota, Japan
A feasibility imager chip of a 32 x 4-pixel array was developed in a 0.18-μm CMOS process for a small size automotive laser imaging detection and ranging. Each pixel consists of 8 single-photon avalanche diodes as a world-first 2-D pixel array with digital output macro pixel architecture which enables laser signal sensing under sunlight noise. Distance measurement results show less than 2.1% nonlinearity and 0.11-m standard deviation up to 20-m distance with 10%-reflective target under the ambient light of 75 klux.

A 16.5 Giga Events/s 1024 × 8 SPAD Line Sensor with Per-Pixel Zoomable 50ps-6.4ns/bin Histogramming TDC,
A. T. Erdogan, R. Walker, N. Finlayson, N. Krstajić, G. O. S. Williams and R. K. Henderson, Univ. of Edinburgh, UK
A 1024 × 8 single photon avalanche diode (SPAD) based line sensor for time resolved spectroscopy is implemented in 0.13μm imaging CMOS with 23.78 μm pixel pitch at 49.31% fill factor. The line sensor can operate in single photon counting (SPC) mode (65 giga-events/s), time-correlated single photon counting (TCSPC) mode (194 million events/s) or histogramming mode (16.5 giga-events/s), increasing the count rate up to 85 times compared to TCSPC operation. This performance is enabled by a 512 channel histogramming TDC with 50ps-6.4ns/bin zoomable time resolution.

A 272.49 pJ/pixel CMOS Image Sensor with Embedded Object Detection and Bio-Inspired 2D Optic Flow Generation for Nano-Air-Vehicle Navigation,
K. Lee, S. Park, S.-Y. Park, J. Cho and E. Yoon, Univ. of Michigan, USA
We report a CMOS imager embedded with energy-efficient object detection and bio-inspired 2D optic flow generation cores for navigation of nano-air-vehicles (NAVs). The proposed vision-based navigation system employs spatial difference imaging and gradient orientation using mixed-signal circuits to achieve both energy-efficient and area-efficient implementation. The system achieved 272.49 pJ/pixel with 75% reduction in memory size for integrated operation of object detection and 2D optic flow generation.

Demo Sessions:
  • A Shutter-Less Micro-Bolometer Thermal Imaging System Using Multiple Digital Correlated Double Sampling for Mobile Applications,
    S. Park, T. Cho, M. Kim, H. Park, and K. Lee, KAIST and Seoul National Univ. of Science and Technology, Korea
  • A 4.1Mpix 280fps Stacked CMOS Image Sensor with Array-Parallel ADC Architecture for Region Control,
    T. Takahashi, Y. Kaji, Y. Tsukuda, S. Futami, K. Hanzawa, T. Yamauchi, P. W. Wong, F. Brady, P. Holden, T. Ayers, K. Mizuta, S. Ohki, K. Tatani, T. Nagano, H. Wakabayashi, and Y. Nitta, Sony, Japan and Sony, USA
  • 320x240 Back-Illuminated 10µm CAPD Pixels for High Speed Modulation Time-of-Flight CMOS Image Sensor,
    Y. Kato, T. Sano, Y. Moriyama, S. Maeda, T. Yamazaki, A. Nose, K. Shina, Y. Yasu, W. van der Tempel, A. Ercan and Y. Ebiko, Sony, Japan and SoftKinetic, Belgium

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