More Details from Sony IEDM 2017 Presentation

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Fuse publishes few more slides from Sony presentation on 3-layer chip stacking flow at IEDM 2017.

"The final product is an impressive 19.3M pixels of 1.22 x 1.22 μm each and a 1 Gbit DRAM. Sony used TSVs that have a minimum diameter of 2.5 μm and a pitch of 6.3 μm with a line of 2 μm and space of 0.64 μm. In total they have over 35,000 TSVs – about 15,000 connecting the pixel substrate and the DRAM substrate and about 20,000 more connecting the DRAM substrate to the logic substrate.

The chip achieved 120 fps for all 19.3M pixels and can produce 960 fps FHD (1,920 x 1,080) super slow motion video.
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3-layer stacking process flow
TEM cross-section

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