MIPI D-PHY v.3.0 Standard Increases Speed to 11Gbps per Lane

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The MIPI Alliance announces a major update to its MIPI D-PHY specification for connecting megapixel cameras and high-resolution displays to application processors. Version 3.0 doubles the data rate of D-PHY’s standard channel to 9 Gbps for the standard channel (and 11 Gbps for its short channel), while extending the power efficiency of the specification.

In tandem with the boost in data rate, D-PHY v3.0 introduces a Continuous-Time Linear Equalizer (CTLE) on the receiver side of a connection to maintain the interface’s superior power efficiency. D-PHY v3.0 is fully compatible with previous versions of the MIPI specification.

Pixel rates in camera and display applications are constantly increasing, and v3.0 of D-PHY provides the leap in data rate necessary to support next-generation image sensors while extending the specification’s low-power attribute,” said Joel Huloux, chairman of MIPI Alliance. “MIPI continues to innovate its PHY interfaces to enable advancements in camera and display applications and emerging market dynamics.

In conjunction with the release of D-PHY v3.0, MIPI Alliance also announces version 2.1 of MIPI C-PHY, which provides high throughput and superior power efficiency to connect displays and cameras to application processors. The specification supports symbol rates up to 6 Gigasymbols per second (Gsps), equivalent to 13.7 Gbps, over the standard channel and up to 8 Gsps over the short channel. A new 64-bit PHY Protocol Interface (PPI) in v2.1 provides a wider bus between C-PHY and a chip’s core logic for better support of higher-performance applications. The new version of the interface is fully compatible with previous versions of C-PHY.

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